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Title: Digital ASIC Design Engineer 4
Location: United States-Maryland-Baltimore
Other Locations: null
Specifically this position requires physical design of digital and mixed signal ASIC designs targeting deep submicron foundry processes. Physical design shall include all synthesis, floorplanning, placement, routing, clock tree synthesis, static timing analysis and LVS/DRC steps required to generate GDS from RTL.
Minimum of 10 years of ASIC physical design experience with at least 10 successful tapeouts; experience with 90nm or smaller feature sizes; experience with Cadence Design Implementation, Synopsys Design Compiler, Synopsys PrimeTime, Mentor Graphics Calibre, Cadence Virtuoso, Cadence Conformal, Cadence QRC; requires a current or active Secret Clearance with the ability to obtain higher level clearances. Bachelors Degree required.
Experience with IBM foundry technologies; experience with Trusted Foundry program; experience with System on Chip ASIC architecture; experience with RTL design and simulation; experience with Synopsys IC Compiler.
Northrop Grumman Corporation is a leading global security company providing innovative systems, products, and solutions in aerospace, electronics, information systems and technical services to government and commercial customers worldwide.
Northrop Grumman is committed to hiring and retaining a diverse workforce. We are an Equal Opportunity Employer, making decisions without regard to race, color, religion, sex, national origin, age, veteran status, disability, or any other protected class. U.S. Citizenship is required for most positions.